1. Field of Invention
The present invention relates to a low reference voltage generating circuit, and more particularly to a circuit that can provide a stable voltage lower than one volt.
2. Related Art
For the circuit design of portable products, besides the requirement of small size, an important consideration is the maximum reduction of the power consumed because the power supply for such portable products is a battery.
With reference to FIG. 5, a voltage generating circuit in accordance with the prior art comprises a current mirror (40), a voltage generating unit (45) and a start-up unit (50). The start-up unit (50) prevents FETs and transistors in the current mirror (40) and the voltage generating unit (45) to be biased at cutoff region. The current mirror (40) is made up of two P-channel FETs (Q1, Q2), two N-channel FETs (Q3, Q4), two PNP transistors (Q5, Q6) and a resistor (R1). The voltage generating unit (45) has a P-channel FET (Q7), a varistor (VR1) and a PNP transistor (Q8). The P-channel FET (Q7) has a gate that is connected to the current mirror (40) and a source that is connected to the PNP transistor (Q8) through the varistor (VR1). An output terminal, denoted with VO, is taken from the source of the P-channel FET (Q7).
When each FET and each transistor is well biased, the current mirror (40) generates a first current (I1) and a second current (I2). By properly choosing the matched FETs and transistors in the current mirror (40), the second current (I2) is approximately equal to the first current (I1), and the voltage value at nodes X and Y (respectively denoted by Vx and Vy) are also approximately the same. The first current (I1) is represented:
I1=(Vxxe2x88x92VBEQ5)/R1
=(Vyxe2x88x92VBEQ5)/R1
=(VBEQ6xe2x88x92VBEQ5)/R1
where VBE represents the junction voltage at the base-emitter junction of a transistor.
Further the junction voltage VBE can be represented as VBE=VTxc3x97ln (k), where VT is the thermal voltage and is equal to approximately 25 mV at room temperature.
Thus, the first current (I1) is rewritten as:
I1=[VTxc3x97ln(kQ6)xe2x88x92VTxc3x97ln(kQ5)]/R1
=[VTxc3x97ln(kQ6/kQ5)]/R1
=[VTxc3x97ln(n)]/R1
where n=kQ6/kQ5 is the character ratio of the two PNP type transistors (Q5 and Q6)
Furthermore, an output current (I3) flowing through the FET (Q7) of the voltage generating unit (45) is approximately equal to the first current (I1).
Thus the output voltage VO is
VO=I3xc3x97R2+VBEQ8.
When further combining the foregoing equation I1=[VTxc3x97ln(n)]/R1 with VO=I3xc3x97R2+VVBEQ8, the output voltage is obtained by the equation, VO=VBEQ8+VTxc3x97ln(n)xc3x97(R2/R1).
The minimum value of the output voltage VO generated by the conventional circuit is still approximately 1.2 volts. In the field of high density integrated circuit design, the operating voltage of the elements in the integrated circuits is intended to be maintained as low as possible to reduce power consumption. Therefore, a constant voltage lower than 1.2 volts is necessary to be used with integrated circuits.
To overcome the shortcomings, a voltage generating circuit in accordance with the present invention obviates or mitigates the aforementioned problems.
The primary objective of the voltage generating circuit in accordance with the present invention is to provide a stable voltage lower than one volt to meet the need for a low operating voltage in integrated circuit design.
To achieve the objectives, the voltage generating circuit comprises a first current mirror, a second current mirror and a voltage generating unit. The first current mirror generates a first current. The second current mirror is connected to the first current mirror to generate a second current that is proportional to the first current. The voltage generating unit consists of three resistors in a T-shaped configuration. An output voltage node is taken from the T-shaped configuration to provide a voltage lower than 1 volt.
Other objects, advantages and novel-features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.